COOLRUNNER ii

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En este ejemplo de diseño, el interruptor Pmod va en el puerto J8, el PS/2 Pmod va en puerto J7, y un display de siete segmentos Pmod va en puertos J5 y J6. Por supuesto, el diseño se puede cambiar para utilizar diferentes puertos.

El CPLD implementa un contador, así como un decodificador de teclado PS/2. El display cambia entre los dos valores de SW4. Los SW1, 2, y 3 no se utilizan en el diseño. BTN0 es el reset del sistema para el diseño.

Cuando SW4 tiene el decodificador PS/2 seleccionado, la salida en la pantalla es el código de exploración para esa letra. He aquí algunos códigos de exploración, el resto se puede encontrar en Internet.

[pic 5]

Recomendaciones de Diseño

- El regulador ofrece Vccio de 3.3V, también fijado por Default I/O Standard apropiado.

- No utilizados de I/O se debe establecer en la tierra para minimizar la fuente.

- Terminación de entrada se debe fijar para reducir al mínimo el consumo de energía en los pines de entrada potencialmente flotantes.

Software Installation

A Windows based CoolRunner-II Utility Window software application is provided with

the CoolRunner-II evaluation board. This application is used to program the CPLD, change security settings, and monitor board current and temperature. This application should be installed prior to connecting the board to a PC so that Windows will recognize the board the first time it is plugged in. At this time, Windows XP and Vista (32-bit versions) are the only supported operating systems for the Utility Window software.

Upon opening the package, you can easily test the board for basic functionality by performing the following steps:

1. Insert the Resource CD and click on ‘Software Install’ to install the CoolRunner-II Utility Window software.

2. Attach the USB connector to a computer and the board. On the initial connection to the USB port, the Add New Hardware Wizard will appear and ask you to install the driver.

When prompted, select to install the driver automatically. Once installed, the 3.3V supply LED (LD5) on the CoolRunner-II board should light to show that the regulator is enabled and the CPLD is powered.

3. Start the CoolRunner-II Utility Window from : Start → Programs → Digilent → Tools

4. Press the Start button to begin viewing the power consumption for the device. In order to program the CPLD, the ISE WebPACK software must also be installed.

1. Insert the ISE WebPACK DVD and run the install program.

2. Re-boot the PC.

3. Ensure that the CoolRunner-II Evaluation Board is connected to the PC.

4. Start the CoolRunner-II Utility Window program from: Start → Programs → Digilent → Tools

5. After the CoolRunner-II Utility Window appears, press the Browse button (shown in Figure 1-3) and navigate to the desired JED file. (The demonstration JEDEC file is present on the resource CD at /CR-II_board_files/demomain/top.jed).

[pic 6]

6. Press the Program button to configure the CPLD (Erase will happen automatically

and does not need to be performed in advance of programming).

Demonstration Design

The design pre-programmed into the CPLD acts as the LCD module driver, as well as implements a simple timer. The right-most two digits of the 7-segment display represent time in seconds, the left-most two digits represent minutes. LED3 is a ‘heartbeat’ that pulses every second. BTN0 is a push-button reset for the counter. BTN1 is a push-button pause for the counter and LED display. SW0 is a slide switch for the DataGATE control signal. The design is intended to operate with a clock frequency of 1 MHz (JP1 set to bottom two pins). The design will still function with slower clock frequencies, but the counter will operate slower and the 7-segment display will not refresh at a sufficient rate.

Without the LCD module installed, power the board and start the CoolRunner-II Utility Window. Begin taking power measurements in the software. Notice how the power changes when you change the position of clock frequency jumper (JP1). Naturally, the faster clock results in increased power consumption. Now press and hold BTN0 (reset).

Notice a slight power reduction on VCCINT, as internal counters are held in reset. VCCIO is relatively unchanged, as the input clock is still causing the input buffer to toggle. Next, enable the DataGATE feature by sliding SW0 to the left. This blocks the clock signal from the CPLD, so the design will halt operation. You will see power drop for VCCINT to quiescent levels (in the 20 μA range). VCCIO also decreases as I/O power is saved by using DataGATE. When you switch SW0 back to the right, note that the counter picks up where it left off; you do not lose design data by entering this low power mode.

You should observe that the power change is gradual, and not instantaneous. This is a result of the Average Filter option. This option is set to average out the curve displayed on the screen. This is desired because the current is sampled roughly once a second, and the power consumption of the device could be higher or lower than the average depending on the active state of the design. For example, a circular shift register would have consistent power measurements since the number of signals toggling every clock cycle is identical, whereas a binary counter would not be consistent.

Now, plug the LCD module into ports J3 and J4. Press the reset button (BTN0) and the LCD will initialize and scroll ‘Xilinx CoolRunner-II’ across the display.

Configuration

The CPLD on the CoolRunner-II Evaluation Board has been pre-programmed with the project named ‘Demomain’. You can modify this design or create your own design from schematics or HDL source files using the free ISE™ WebPack software from Xilinx.

Configuration files can be transferred to the CoolRunner-II Evaluation Board using a USB cable and the CoolRunner-II Utility Window software, or using an external programming cable (not provided) and Xilinx’s iMPACT